The present invention relates to electronics, and more particularly, to a pair of complementary current sources.
FIG. 1 illustrates a pair of complementary current sources of a known type. The pair of current sources includes a reference current source I1 and three current mirrors M1, M2 and M3. The pair of complementary current sources is such that the sum of complementary currents is substantially equal to the current of the reference source. The pair of complementary current sources is connected between two supply terminals 7 and 8. The first supply terminal 7 is set to a high potential Vcc, and the second supply terminal 8 is set to a low potential Vee, which is generally ground.
In the example, the reference current source I1 is connected between supply terminal 7 set to a high potential Vcc, and to the first current mirror M1 and to the second current mirror M2. The current source I1 delivers a current Iref, and is relatively straightforward to make.
The first current mirror M1 includes a master branch 1 with a diode connected bipolar mirror transistor T1, and a slave branch 2 with a bipolar mirror transistor T2. It is assumed that both transistors T1, T2 are of the NPN type. The bases of both transistors T1, T2 are connected together, and the emitters of both transistors T1, T2 are connected to the supply terminal 8 set to a low potential Vee. The collector of transistor T1 is connected to the base thereof, and to the reference current source I1. The collector of transistor T2 supplies an incoming current IN.
The second current mirror M2 includes a master branch 3 with a diode connected bipolar mirror transistor T3, and a slave branch 4 with a bipolar mirror transistor T4. It is assumed that both transistors T3, T4 are of the NPN type. The bases of both transistors T3, T4 are connected together, and the emitters of both transistors T3, T4 are connected to the supply terminal 8 set to the low potential Vee. The collector of transistor T3 is connected to the base thereof, and to the reference current source I1. The collector of transistor T4 is connected to the third current mirror M3.
The third current mirror M3 includes a master branch 5 with a diode connected bipolar mirror transistor T5, and a slave branch 6 with a bipolar mirror transistor T6. It is assumed that both transistors T5, T6 are of the PNP type. The third mirror is complementary to the first one M1.
The bases of both transistors T5, T6 are connected together, and the emitters of both transistors T5, T6 are connected to the supply terminal 7 set to the high potential Vcc. The collector of transistor T5 is connected to the base thereof, and to the collector of transistor T4 of the second current mirror M2. The collector of transistor T6 supplies an outgoing current IP.
As a result of such a current mirror arrangement, current Iref of the current source I1 is substantially the sum of the incoming IN and outgoing IP currents. Each of the sources of the pair is to bias complementary transistors. These transistors are made at the same time as those of the current mirrors of the source pair. Identical bipolar transistors of the same type, e.g., NPN, thus have identical features and in particular the same current gain xcex2N. However, the current gains xcex2N and xcex2P of the two complementary transistors are not equal.
For some applications, in particular rail-to-rail long-tail pair connections, the bases of both complementary transistors NPN and PNP are connected together and set to the same potential. To improve accuracy and obtain reduced offset voltage, it is desired to cancel the base current of the NPN transistor through the base current of the PNP transistor, i.e., the quantity IN/xcex2N is to be substantially equal to the quantity IP/xcex2P. This is not possible with a pair of current sources as illustrated in FIG. 1.
In view of the foregoing background, an object of the present invention is to provide a pair of complementary current sources, with one current source for biasing at least one transistor and the other current source for biasing at least one transistor of a complementary type.
This and other objects, advantages and features according to the present invention are provided by a pair of complementary sources formed by a reference current source, and two complementary current mirrors having complementary bipolar transistors. The complementary transistors supply the complementary currents so that the sum of the complementary currents is substantially equal to the reference current of the reference current source, and so that the base currents of the complementary transistors compensate for each other.
Thus, when using such a pair of complementary sources for biasing complementary bipolar transistors, their base currents will compensate for each other. For this purpose, the pair of complementary current sources comprises a reference current source, and two complementary current mirrors each having a master branch and at least one slave branch. Each branch is provided with a bipolar mirror transistor, and the bases of the mirror transistors of the same mirror are connected together. These complementary current mirrors deliver complementary currents at respective slave branches. The first one of the complementary current mirrors is connected to the reference current source via the master branch thereof.
The pair of complementary current sources further includes an intermediate current mirror having a master branch and at least one slave branch connected to the master branch of the second one of the complementary current mirrors via the slave branch thereof.
The pair of complementary current sources further includes means for mutually trimming the complementary currents. The trimming means is connected between the master branch of the intermediate current mirror and a node common to the bases of the mirror transistors of the complementary current mirrors. This substantially equalizes the base currents of the mirror transistors of the complementary mirrors. The intermediate current mirror is connected to the reference current source via a second slave branch.
The difference between the number of branches of the complementary current mirrors is chosen to be less than or equal to one so that, when the complementary currents are trimmed, the common node is equal to the sum of currents substantially canceled by the effect of the trimming means.
The trimming means of the complementary currents can be made from a common-emitter amplifying transistor, the base of which is connected to the common node. In this configuration, the first one of the complementary current mirrors has one slave branch more than the second one of the complementary current mirrors. The transistor of the trimming means is then of the same type as the mirror transistors of the second one of the complementary current mirrors.
The mirror transistor of the master branch of at least one of the complementary current mirrors can be diode-connected via an additional transistor, with the mirror transistor and the additional transistor having a cascode arrangement. In this configuration, the base of the mirror transistors of at least one of the complementary current mirrors is connected to the common node via the additional transistor. Voltage down-converting means may also be series-connected with the transistor of the trimming means on the emitter-side thereof.
Another aspect of the invention is directed to an integrated circuit comprising complementary transistors and a pair of complementary current sources for biasing the complementary transistors. Such current source pairs are frequently used in the input stages of operational amplifiers and inside comparators.